The present invention relates to a failure detecting method, a failure detecting apparatus, and a semiconductor device manufacturing method.
In order to improve the yield of LSI manufacturing, it is important to analyze the yield loss, early clarify the process, manufacturing apparatus, or design condition that is the cause of the yield loss, and improve it. However, since an LSI is produced through several hundred steps and manufacturing apparatuses, identifying the cause of LSI failures is very difficult work.
For the clarification of the cause of failures, the results of an electrical property test (a die sort test) that is performed after the wafer process is finished may be used. The die sort test includes, for example, a DC test for examining the current consumption of an integrated circuit, a function test for confirming the desired operation of an integrated circuit, and a margin test for checking the allowable operation range of an integrated circuit.
This die sort test is performed with the wafer in a round shape, and the test results are mapped and displayed at positions in the wafer surface. For example, for a memory product, such as a DRAM, the test results are expressed by an FBM (Fail Bit Map). Also, a pass/fail map in which a pass or fail per chip is mapped and displayed is obtained.
Failure distribution in the wafer surface is largely divided into two types, random failures evenly distributed without depending on the position on the wafer surface, and clustering failures causing unbalance somewhere. Among these, for the clustering failures, the factor of the clustering failures is often due to a process, a manufacturing apparatus, and the like, and the clustering failures are a great cause of yield decrease.
It is indicated that failures caused by a process and a manufacturing apparatus leave “a fingerprint” as failure distribution on the wafer surface. In other words, if a problem occurs in a certain process and manufacturing apparatus, clustering failures specific to the process and manufacturing apparatus occur. In this sense, it can be said that classifying the clustering failures is a clue to the clarification of the cause of failures.
A failure analyzing method is proposed in which the processing process that is the cause of failure occurrence is identified by performing appearance inspection after each processing process in a wafer processing process to create a predicted probe inspection map considering that a chip corresponding to a place where a defect is detected will be a failed chip, performing probe inspection after the wafer processing process to perform pass/fail determination for each chip to create a probe inspection map, and extracting the predicted probe inspection map matching or similar to the probe inspection map (see, for example, Japanese Patent Laid-Open No. 2005-236094).
However, since not all chips corresponding to the places where a defect is present are failed, it is difficult to identify the processing process that is the cause of failure occurrence by comparison of the predicted probe inspection map and the probe inspection map.
It is desired to automatically and efficiently detect the similarity between wafer maps in different data forms, such as the results of the test (the die sort test) after the wafer processing process and the results of the appearance inspection after each processing process, and early identify the cause of failures with good precision.